A fundamental limit that prevents the scaling of CMOS (complimentary metal oxide) semiconductor processes beyond the physical dimensions of atoms has resulted in an increase in the importance of a low-cost, high-performance multi-chip packages for the design of VLSI (very large scale integrated) circuits. In an embedded system-on-a-chip (SoC) design, different memory and logic circuits on the same substrate often require different processing steps. For example, nonvolatile flash memory uses double poly-silicon floating gates with an ultra thin tunnel oxide, which are not compatible with the conventional CMOS processes for fabricating logic circuits.
In addition, it is difficult to integrate chips that are fabricated on different substrate materials, such as silicon, glass, silicon carbide (SiC), gallium arsenide. (GaAs), and other compounds of groups III-V. The integration of specific integrated circuits (ASIC) with devices such as magnetic random access memory (MRAM) and micro-electro-mechanical systems (MEMS) presents further challenges in the design of multi-chip packages.
For example, in a two-dimensional multi-chip package, chips are placed horizontally on a carrier and global interconnects are formed on top of the chips, or on a second-level package. However, due to the variation of chip thickness, it is often necessary to planarize the bonded chip surface, and the gaps between the chips and the surrounding areas. Without a flat surface, interconnect processes based on a Damascene method cannot be properly preformed on a bonded chip surface. Furthermore, without critical alignment control, each carrier will need to have a customized mask set to form global interconnects, which increases the manufacturing cost.
Further, in a three-dimensional stacked-chip package where two or more chips are stacked vertically, interconnections among stacked chips are formed at the edges of each chip using a wire bond or a tag bond. Stacked chips that are used in portable devices must be thinned down in order to fit into the limited space available. As the number of stacked chips increases, the thickness of the chips must be reduced. The number of chips that can be stacked is determined by the maximum available space and the minimum chip thickness.
Therefore, a need exists for economical and cost effective method of forming a multi-chip wafer-level chip packages without the need for planarizing a bonded chip surface in order to form global interconnects and for facilitating the integration of chips fabricated by different processing steps and with different materials.